Extremely high voltages can develop in the vicinity of an integrated circuit due to the build-up of static charges. A high potential may be generated to an input or output buffer of the integrated circuit, which may be caused, for example, by a person touching a package pin that is in electrical contact with the input or output buffer. When the electrostatic charges are discharged, a high current is produced at the package nodes of the integrated circuit, and is referred to as electrostatic discharge (ESD).
ESD is becoming a serious problem for semiconductor devices as the demand for higher operating speed, smaller operating voltages, higher packing density and reduced cost drives a reduction of all device dimensions. This generally implies thinner dielectric layers, higher doping levels with more abrupt doping transitions, and higher electric fields—all factors that contribute to an increased sensitivity to damaging ESD events.
FinFET technology is becoming more prevalent as device size continues to shrink. It is therefore desirable to have an improved structure and fabrication process for forming ESD-tolerant devices compatible with the formation of FinFET structures.